Current and future generation DRAM and SDRAM applications utilize very high I/O speeds. This is particularly true in graphics memory, such as current and future generation GDDR5/GDDR5X specifications. Graphics memories are designed for applications requiring high bandwidths and high I/O speeds, for example, in excess of 8 Gbps. However, current and next generation chips, such as GDDR5 for example, employ narrower memory interfaces, such as narrower memory bus widths, and reduced chip size relative to previous generations.
Increasing speeds and smaller footprints generally result in smaller signal amplitude and smaller data valid windows. With smaller data valid windows, small voltage biases inherent in an I/O interface may cause data to be unreliably communicated between a host and a memory.